Embodiments of the present invention relate to an Electrically Erasable Programmable Read Only Memory (EEPROM) array architecture for a cell having a single polycrystalline silicon gate.
Contemporary semiconductor integrated circuits typically perform much more complex functions than previous designs. Mixed mode circuits performing combined analog, digital, and memory functions are common for many applications. At the same time these mixed mode circuits must keep the manufacturing process as simple as possible to reduce cost and improve the process yield. A single polycrystalline silicon EEPROM cell of the prior art that may be compatible with existing complementary metal oxide silicon (CMOS) processes is illustrated at FIG. 10. The cell includes complementary floating gates 1012 and 1014 which serve as control gates for respective sense transistors. During a read operation, these sense transistors are accessed by read select transistors which connect the sense transistors to bit line (BL) and complementary bit line (BL_) terminals. Each cell includes a control circuit 1020 which receives global address and control signals and produces local control signals for the respective cell. Programming is accomplished, for example, by driving WR1_low, WR_EN1 high, and WR_EN2 low. In this state, N-channel transistor 1008 is on and N-channel transistor 1010 is off. Reference transistors 1004 and 1006 couple low and high signals between respective P-channel and N-channel transistors. Responsively, P-channel transistor 1002 is on and P-channel transistor 1000 is off. This programs positive charge on floating gate 1012 and negative charge on floating gate 1014. One disadvantage of this cell is that it requires a separate control circuit 1020 for each cell. Another disadvantage is that it requires substantial layout area for the complementary floating gates 1012 and 1014. Yet another disadvantage of this cell is that transistors 1004 through 1010 are constructed as large drain-extended transistors indicated by asterisks to preclude punch through at relatively high drain-to-source voltages.
Other single polycrystalline silicon EEPROM cells of the prior art may be manufactured together with analog and digital circuits on a single integrated circuit. Such EEPROM cells permit nonvolatile memory to be formed in mixed mode circuits for many applications. Chi et al. (U.S. Pat. No. 5,940,324) and Chen et al. (U.S. Pat. No. 6,930,002) both developed single polycrystalline silicon EEPROM cells that are programmed by band-to-band tunneling. The present inventors have developed an improved array architecture for a single polycrystalline silicon EEPROM cell that offers several advantages over single polycrystalline silicon memory cells of the prior art as will become apparent in the following discussion.